Founded in 2017, Pensando Systems is pioneering distributed computing designed for the New Edge - powering software-defined cloud, compute, networking, storage and security services to transform existing architectures into the secure, ultra-fast environments demanded by next generation applications.
The Pensando platform, a first of its kind, was developed in collaboration with the world’s largest cloud, enterprise, storage, and telecommunications leaders and is supported by partnerships with HPE, NetApp, Equinix, and multiple Fortune 500 customers.
Pensando is led by Silicon Valley’s legendary “MPLS” team — Mario Mazzola, Prem Jain, Luca Cafiero, Soni Jiandani and Randy Pond — who have an unmatched track record of disruptive innovation having already built 8 $Bn/Year businesses across storage, switching, routing, wireless, voice/video/data, & software-defined networking.
As a Signal Integrity & Power Integrity Validation Engineer you will participate in the definition and implementation of the initial framework, and perform feasibility study for complex high-speed designs with leading edge high speed and high-power consumption. Signal Integrity engineers Validation Engineer will contribute in all phases of the product design, including definition, review and signoff on schematics, bring up of a new ASIC. and validating the design in the lab through lab measurements. In this position, you will:
- Work with the HW, ASIC, SW, and FW teams to provide signal and power integrity needed for the product
- Work alongside simulations for SoC package, and PCB designs, while working with cross functional teams to optimize the design for performance, quality, and correctness
- Develop simulation methodologies, and design sign off checklists
- Participate and drive lab measurement activates, to correlate the simulations to physical reality, at the same driving improvements in methodologies for correlation
- Work with fab vendors, IP, components, and ASIC vendors in finding best in class solutions for our products
- Be a team player, quality driven, and effective communicator
- 3+ years of experience in high speed designs with signal integrity focus
- Ability to programmatically automate repetitive tasks in your day to day job (knowledge in scripting languages is highly desired: TCL, Python, etc.)
- Experience with EDA tools such as Ansys HFSS, Cadence PowerSI, Q3D, PowerDC, APD, Keysight ADS, HSpice, and SIWave
- Experience in high speed SerDes
- Strong electrical debug capabilities, having the technical breadth and depth to gap various functional teams
- Familiarity with high-speed serial interfaces such as: XFI, KR, and PCIe
- Familiar with memory interfaces such as DDR4, and DDR5. Ability to do timing analysis
- Ability to direct CAD with design constraints, and routing rules
- Hands on lab measurements, validation process. Correlation on package, and PCB level
- Trade off studies around ASIC die bump-out, package pin-out/ball-out assignment
- Familiar with industry standard lab tools such as: real time scopes, VNA, TDR, and BERT
- Excellent oral and written communication skills
- MSEE or equivalent practical experience, with minimum 3+ years of work experience