MTS - ASIC Physical Design (800-109)

Remote US, Full time

 

Experience:

You will lead the backend physical development of complex ASICs, working closely with the RTL designers and silicon vendors. Responsibilities include developing methodology and automated infrastructure for the following:

  • Hierarchical synthesis in DC and Genus 
  • Managing the synthesis of dozens of blocks for an entire ASIC
  • Managing physical timing closure on 1GHz+ designs
  • Innovus initial floorplanning 
  • Weekly congestion and timing reviews and improvements with RTL designers
  • Block level floorplan optimization feedback to vendor
  • Netlist quality checkers
  • Lint and Cross clock domain checking
  • Formal equivalence RTL to Synthesized netlist, Synthesized to Post place and route
  • STA constraints generation and review with designers, Running STA
  • Generating Netlist ECOs

Must haves:

  • Expert in scripting languages
  • Expert in developing infrastructure for multi-user ASIC physical Design tools
  • Strong communication skills

Keywords: 

  • ASIC, scripting, synthesis, innovus, formal, primetime, CDC, linting

Requirements: 

Languages: TCL, Perl, Python

Tools: Spyglass/Lint, CDC, Formality, Conformal, Synthesis, DC-Shell, Genus, Innovus, Primetime

Education: BSEE or equivalent. MSEE preferred

Experience: 5 years

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