Signal Integrity Engineer (600-102)

Pensando HQ, Full time

Job Requirements:

As a Signal Integrity & Power Integrity Engineer you will participate in the definition and implementation of the initial framework, and perform feasibility study for complex high-speed designs with leading edge high speed and high-power consumption. Signal Integrity engineer will contribute in all phases of the product design, including definition, review and signoff on schematics, bring up of a new ASIC. In this position, you will:


      Work with the HW, ASIC, SW and FW teams to provide signal and power integrity needs for the product

      Perform simulations for SoC package, and PCB designs, while working with cross functional teams to optimize the design for performance, quality, and correctness

      Develop simulation methodologies, and design sign off checklists

      Participate and drive lab measurement activates, to correlate the simulations to physical reality, at
the same driving improvements in methodologies for correlation

      Work with fab vendors, IP, components, and ASIC vendors in finding best in class solutions for
our products

      Be a team player, quality driven, and effective communicator


Preferred Qualifications:

      3+ years of experience in high speed designs with signal integrity focus 

      Ability to programmatically automate repetitive tasks in your day to day job (knowledge in scripting languages in highly desired: TCL, Python, etc)

      Experience with EDA tools such as Ansys HFSS, Cadence PowerSI, Q3D, PowerDC, APD, Keysight ADS, HSpice, and SIWave

      Experience in high speed SerDes

      Strong electrical debug capabilities, having the technical breadth and depth to gap various
functional teams

      Familiarity with high-speed serial interfaces such as: XFI, KR, and PCIe

      Familiar with memory interfaces such as DDR4, and DDR5. Ability to do timing analysis

      Ability to direct CAD with design constraints, and routing rules

      Experience in model extraction, frequency and time domain

      Hands on lab measurements, validation process. Correlation on package, and PCB level

      Trade off studies around ASIC die bump-out, package pin-out/ball-out assignment

      Familiar with industry standard lab tools such as: real time scopes, VNA, TDR, and BERT

      Excellent oral and written communication skills


Education Requirements:


      MSEE or equivalent practical experience, with minimum 3+ years of work experience

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