Description:  Design and architecture responsibilities as part of a small, dynamic ASIC team developing  next generation data center infrastructure.  

Requirements:

Languages and tools:

• Verilog, System Verilog, Perl/Python, C or C++
• Synthesis, Spyglass/Lint, Power optimization, CDC 
• System Verilog simulators and waveform debuggers
• Accelerators/Emulation/FPGA prototyping is a plus

Design experience:

• Developing Microarchitecture and Verilog RTL

• Reviewing Synthesis, Timing, Spyglass/Lint Reports and fix the RTL
• Help develop and review the test plans, tests and coverage reports to create a robust tape-out

Domain knowledge:

• Experience with design and development of peripherals and storage devices
• Experience with integration of external IPs for SOC subsystems
• Experience with integration and debug of processors such as ARM, MIPS or RISC-V
• Experience with integration and debug of NOC and Coresight components
• Experience with secure boot, Root-of-trust (ROT) methodologies is a plus
• Be well versed in interface timing budget & clock domain crossing design
• Working knowledge of timing and debug from the ASIC through the board to peripherals

Other qualifications:

• Solid knowledge and understanding of Computer Architecture
• Passionate and analytic with excellent technical problem-solving skills
• Ability to manage multiple tasks and work toward long-term goals
• Excellent communication skills (verbal and written)