MTS - ASIC Design (800 - 102/103)

Pensando HQ, Full time

Requirements

Languages: Verilog, System Verilog, C or C++

Tools: Synthesis, Spyglass/Lint 

Experience:
Have been responsible for designing complex logic blocks for at least 2 chips.
Responsibilities include:
  • Developing Microarchitecture 
  • Developing the RTL 
  • Reviewing Synthesis, Timing, Spyglass/Lint Reports and fix the RTL
  • Working with verification team to develop and review the test plan, tests and coverage reports to create a robust tape-out.

Highly Desirable:
  • Having developed a block from scratch that has features that were built for the first time
  • Knowledge of Data Structures and/or Coding Theory 

Domains of Past Employers
Data Center Storage, CPU or Networking
 
Education: BSEE or equivalent. MSEE preferred

Experience: 5 years
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