Languages: Verilog, System Verilog, C or C++
Tools: Synthesis, Spyglass/Lint
Have been responsible for designing complex logic blocks for at least 2 chips.
Developing the RTL
Reviewing Synthesis, Timing, Spyglass/Lint Reports and fix the RTL
Working with verification team to develop and review the test plan, tests and coverage reports to create a robust tape-out.
Domains of Past Employers
Data Center Storage, CPU or Networking
Education: BSEE or equivalent. MSEE preferred
Experience: 5 years