MTS - ASIC Verification (800-100/101)

Pensando HQ, Full time

 
Requirements

Languages: UVM, SystemVerilog, C or C++

Tools: SystemVerilog simulators and waveform debuggers

Required qualifications
• MS in Electrical or Computer Engineering with 2+ years of relevant industry experience, or BS with 4+ years of experience
• Experience developing and executing test plans for Unit/IP/Sub-system/SOC level verification
• Experience in System Verilog test bench development including stimulus, checkers, transactors/BFMs, assertions and coverpoints
• Experience identifying bugs in architecture, functionality and performance with strong overall debug and analytical skills
• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy/DVE)

 

Preferred Qualifications
• Experience in UVM 
• Proficient with scripting languages, C/C++
• Experience using multiple verification platforms: FPGA, emulator, software environments and/or post-silicon
• Great communication and collaboration skills to interact within the team and with cross functional teams

Domains of Past Employers
CPU or Networking preferred but not required
 
Education: BSEE or equivalent. MSEE preferred

Experience: 4 years
 
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